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1996 data sheet m pd75p3036 mos integrated circuit 4-bit single-chip microcontroller the m pd75p3036 replaces the m pd753036s internal mask rom with a one-time prom or eprom. because the m pd75p3036 supports programming by users, it is suitable for use in prototype testing for system development using the m pd753036 and for use in small-scale production. caution the m pd75p3036kk-t is not designed to guarantee the reliability required for use in mass- production. please use it only for performance evaluation during testing and test production runs. detailed descriptions of functions are provided in the following document. be sure to read the document before designing. m pd753036 users manual : u10201e features ? compatible with m pd753036 ? internal prom: 16384 8 bits ? m pd75p3036kk-t : reprogrammable (ideally suited for system evaluation) ? m pd75p3036gc, 75p3036gk : one-time programmable (ideally suited for small-scale production) ? internal ram: 768 4 bits ? can operate in the same power supply voltage as the mask version m pd753036 ?v dd = 1.8 to 5.5 v ? lcd controller/driver ? a/d converter caution mask-option pull-up resistors are not provided in this device. ordering information part number package internal prom quality grade m pd75p3036gc-3b9 80-pin plastic qfp one-time prom standard (14 14 mm, 0.65-mm pitch) m pd75p3036gk-be9 80-pin plastic tqfp one-time prom standard (fine pitch) (12 12 mm, 0.5-mm pitch) m pd75p3036kk-t 80-pin ceramic wqfn eprom not applicable document no. u11575ej1v0ds00 (1st edition) (previous no. ip-3657) date published november 1996 p printed in japan the information in this document is subject to change without notice. in this document, the term prom is used in parts common to one-time prom versions and eprom versions. * * please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. the mark shows major revised points. *
2 m pd75p3036 functional outline parameter function instruction execution time ? 0.95, 1.91, 3.81, 15.3 m s (main system clock: during 4.19-mhz operation) ? 0.67, 1.33, 2.67, 10.7 m s (main system clock: during 6.0-mhz operation) ? 122 m s (subsystem clock: during 32.768-khz operation) internal memory prom 16384 8 bits ram 768 4 bits general purpose register ? 4-bit operation: 8 4 banks ? 8-bit operation: 4 4 banks input/ cmos input 8 on-chip pull-up resistors can be specified by using software: 27 output cmos input/output 20 port bit port output 8 also used for segment pins n-ch open-drain 8 13 v withstand voltage input/output pins total 44 lcd controller/driver ? segment selection: 12/16/20 segments (can be changed to bit port output in unit of 4; max. 8) ? display mode selection: static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias), 1/3 duty (1/3 bias), 1/4 duty (1/3 bias) timer 5 channels ? 8-bit timer/event counter: 3 channels (16-bit timer/event counter, carrier generator, timer with gate) ? basic interval/watchdog timer: 1 channel ? watch timer: 1 channel serial interface ? 3-wire serial i/o mode ... msb or lsb can be selected for transferring first bit ? 2-wire serial i/o mode ? sbi mode a/d converter 8-bit resolution: 8 channels bit sequential buffer (bsb) 16 bits clock output (pcl) ? f , 524, 262, 65.5 khz (main system clock: during 4.19-mhz operation) ? f , 750, 375, 93.8 khz (main system clock: during 6.0-mhz operation) buzzer output (buz) ? 2, 4, 32 khz (main system clock: during 4.19-mhz operation or subsystem clock: during 32.768-khz operation) ? 2.86, 5.72, 45.8 khz (main system clock: during 6.0-mhz operation) vectored interrupt external: 3, internal: 5 test input external: 1, internal: 1 system clock oscillator ? ceramic or crystal oscillator for main system clock oscillation ? crystal oscillator for subsystem clock oscillation standby function stop/halt mode power supply voltage v dd = 1.8 to 5.5 v package ? 80-pin plastic qfp (14 14 mm) ? 80-pin plastic tqfp (fine pitch) (12 12 mm) ? 80-pin ceramic wqfn * *
m pd75p3036 3 contents 1. pin configuration (top view) ............................................................................................... 4 2. block diagram ......................................................................................................................... 6 3. pin functions ............................................................................................................................ 7 3.1 port pins ................................................................................................................................................ 7 3.2 non-port pins ........................................................................................................................................ 9 3.3 pin input/output circuits ...................................................................................................................... 11 3.4 recommended connection of unused pins ...................................................................................... 14 4. mk i mode and mk ii mode selection function .............................................................. 15 4.1 difference between mk i mode and mk ii mode .................................................................................. 15 4.2 setting of stack bank selection register (sbs) ................................................................................ 16 5. differences between m pd75p3036 and m pd753036 ........................................................ 17 6. program counter (pc) and memory map ....................................................................... 18 6.1 program counter (pc) .......................................................................................................................... 18 6.2 program memory (prom) .................................................................................................................... 18 6.3 data memory (ram) .............................................................................................................................. 20 7. instruction set ....................................................................................................................... 21 8. prom (program memory) write and verify .................................................................. 30 8.1 operation modes for program memory write/verify ......................................................................... 30 8.2 program memory write procedure ...................................................................................................... 31 8.3 program memory read procedure ...................................................................................................... 32 9. program erasure ( m pd75p3036kk-t only) ...................................................................... 33 10. opaque film on erasure window ( m pd75p3036kk-t only) ......................................... 33 11. one-time prom screening .................................................................................................... 33 12. electrical specifications .................................................................................................. 34 13. characteristic curves (for reference only) ........................................................... 49 14. package drawings ................................................................................................................. 51 15. recommended soldering conditions ............................................................................. 54 appendix a. function list of m pd75336, 753036, and 75p3036 .......................................... 55 appendix b. development tools ............................................................................................ 56 appendix c. related documents ............................................................................................ 60 * * * * *
4 m pd75p3036 1. pin configuration (top view) 80-pin plastic qfp (14 14 mm) m pd75p3036gc-3b9 80-pin plastic tqfp (fine pitch) (12 12 mm) m pd75p3036gk-be9 80-pin ceramic wqfn m pd75p3036kk-t caution connect the v pp pin directly to v dd . p73/kr7 80 p72/kr6 79 p71/kr5 78 p70/kr4 77 p63/kr3 76 p62/kr2 75 p61/kr1 74 p60/kr0 73 reset 72 x2 71 x1 70 v pp 69 xt2 68 xt1 67 v dd 66 av ref 65 av ss 64 an5 63 an4 62 an3 61 1 s31/bp7 s30/bp6 s29/bp5 s28/bp4 2 3 4 s27/bp3 5 s26/bp2 6 s25/bp1 7 s24/bp0 8 s23 9 s22 10 s21 11 s20 12 s19 13 s18 14 s17 15 s16 16 s15 17 s14 18 s13 19 s12 20 com0 21 com1 22 com2 23 com3 24 bias 25 v lc0 26 v lc1 27 v lc2 28 p40/d0 29 p41/d1 30 p42/d2 31 p43/d3 32 v ss 33 p50/d4 34 p51/d5 35 p52/d6 36 p53/d7 37 p00/int4 38 p01/sck 39 p02/so/sb0 40 60 an2 an1 an0 p83/an7 p82/an6 59 58 57 56 p81/ti2 55 p80/ti1 54 p33/md3 53 p32/md2 52 p31/sync/md1 51 p30/lcdcl/md0 50 p23/buz 49 p22/pcl/pto2 48 p21/pto1 47 p20/pto0 46 p13/ti0 45 p12/int2 44 p11/int1 43 p10/int0 42 p03/si/sb1 41
m pd75p3036 5 pin identifications p00 to p03 : port0 s12 to s31 : segment output 12-31 p10 to p13 : port1 com0 to com3 : common output 0-3 p20 to p23 : port2 v lc0 to v lc2 : lcd power supply 0-2 p30 to p33 : port3 bias : lcd power supply bias control p40 to p43 : port4 lcdcl : lcd clock p50 to p53 : port5 sync : lcd synchronization p60 to p63 : port6 ti0 to ti2 : timer input 0-2 p70 to p73 : port7 pto0 to pto2 : programmable timer output 0-2 p80 to p83 : port8 buz : buzzer clock bp0 to bp7 : bit port0-7 pcl : programmable clock kr0 to kr7 : key return 0-7 int0, int1, int4 : external vectored interrupt 0, 1, 4 sck : serial clock int2 : external test input 2 si : serial input x1, x2 : main system clock oscillation 1, 2 so : serial output xt1, xt2 : subsystem clock oscillation 1, 2 sb0, sb1 : serial bus 0,1 reset : reset av ref : analog reference v pp : programming power supply av ss : analog ground v dd : positive power supply an0-an7 : analog input 0-7 v ss : ground md0 to md3 : mode selection 0-3 d0 to d7 : data bus 0-7
6 m pd75p3036 2. block diagram port1 p00-p03 4 port2 p10-p13 4 port3 p20-p23 4 port4 p30/md0- p33/md3 4 port5 p50/d4- p53/d7 4 port6 p60-p63 4 port7 p70-p73 4 port8 p80-p83 4 lcd control- ler/ driver s12-s23 12 s24/bp0- s31/bp7 8 com0- com3 4 v lc0 -v lc2 3 bias lcdcl/p30 sync/p31 f lcd v ss v pp reset v dd cpu clock f stand by control x2 x1 xt2 xt1 system clock generator main sub clock divider clock output control fx/2 n pcl/p22 general reg. ram data memory 768 x 4 bits bank sbs sp (8) alu decode and control 8-bit timer/event counter #0 ti0/p13 intt0 a/d converter basic interval timer/ watchdog timer intbt cascaded 16-bit timer/ event counter ti1/p80 intt2 clocked serial interface si/sb1/p03 intcsi interrupt control int0/p10 av ss pto1/p21 watch timer intw buz/p23 f lcd so/sb0/p02 sck/p01 tout0 int1/p11 int4/p00 int2/p12 kr0/p60- kr7/p73 bit seq. buffer (16) 8 program counter (14) prom program memory 16384 x 8 bits cy tout0 p40/d0- p43/d3 port0 4 av ref 8 an0-an5 an6/p82 an7/p83 pto0/p20 8-bit timer/event counter #1 8-bit timer/event counter #2 intt1 ti2/p81 pto2/pcl/p22
m pd75p3036 7 3. pin functions 3.1 port pins (1/2) pin name i/o alternate function 8-bit status i/o circuit function i/o after reset type note 1 p00 input int4 this is a 4-bit input port (port0). no input connection of an on-chip pull-up resistor can be p01 i/o sck specified in 3-bit units by software for p01 to p03. -a p02 i/o so/sb0 -b p03 i/o si/sb1 -c p10 input int0 this is a 4-bit input port (port1). no input -c connection of an on-chip pull-up resistor can be p11 int1 specified in 4-bit units by software. p10/int0 can select noise elimination circuit. p12 int2 p13 ti0 p20 i/o pto0 this is a 4-bit i/o port (port2). no input e-b connection of an on-chip pull-up resistor can be p21 pto1 specified in 4-bit units by software. p22 pcl/pto2 p23 buz p30 i/o lcdcl/md0 this is a programmable 4-bit i/o port (port3). no input e-b input and output can be specified in bit units. p31 sync/md1 connection of an on-chip pull-up resistor can be specified in 4-bit units by software. p32 md2 p33 md3 p40 note 2 i/o d0 this is an n-ch open-drain 4-bit i/o port (port4). yes high m-e when set to open-drain, voltage is 13 v. impedance p41 note 2 d1 also functions as data i/o pin (lower 4 bits) for program memory (prom) write/verify. p42 note 2 d2 p43 note 2 d3 p50 note 2 i/o d4 this is an n-ch open-drain 4-bit i/o port (port5). high m-e when set to open-drain, voltage is 13 v. impedance p51 note 2 d5 also functions as data i/o pin (upper 4 bits) for program memory (prom) write/verify. p52 note 2 d6 p53 note 2 d7 notes 1. circuit types enclosed in brackets indicate schmitt trigger input. 2. low level input leakage current increases when input instructions or bit manipulate instructions are executed. * *
8 m pd75p3036 3.1 port pins (2/2) pin name i/o alternate function 8-bit status i/o circuit function i/o after reset type note 1 p60 i/o kr0 this is a programmable 4-bit i/o port (port6). yes input -a input and output can be specified in bit units. p61 kr1 connection of an on-chip pull-up resistor can be specified in 4-bit units by software. p62 kr2 p63 kr3 p70 i/o kr4 this is a 4-bit i/o port (port7). input -a connection of an on-chip pull-up resistor can be p71 kr5 specified in 4-bit units by software. p72 kr6 p73 kr7 p80 i/o ti1 this is a 4-bit i/o port (port8). no input -e connection of an on-chip pull-up resistor can be p81 ti2 specified in 4-bit units by software. p82 an6 y-b p83 an7 bp0 output s24 these pins are also used as 1-bit i/o port (bit no note 2 h-a port) segment output pin. bp1 s25 bp2 s26 bp3 s27 bp4 output s28 bp5 s29 bp6 s30 bp7 s31 notes 1. circuit types enclosed in brackets indicate schmitt trigger input. 2. bp0 through bp7 select v lc1 as an input source. however, the output levels change depending on the external circuit of bp0 through bp7 and v lc1 . example because bp0 through bp7 are mutually connected inside the m pd75p3036, the output levels of bp0 through bp7 are determined by r 1 , r 2 , and r 3 . * * pd75p3036 v lc1 r 1 on on bp1 bp0 r 2 r 3 v dd m
m pd75p3036 9 3.2 non-port pins (1/2) pin name i/o alternate function status i/o circuit function after reset type note ti0 input p13 external event pulse input to timer/event counter input -c ti1 p80 -e ti2 p81 pto0 output p20 timer/event counter output input e-b pto1 p21 pto2 p22/pcl pcl output p22/pto2 clock output input e-b buz output p23 frequency output (for buzzer or system clock trimming) input e-b sck i/o p01 serial clock i/o input -a so/sb0 i/o p02 serial data output input -b serial data bus i/o si/sb1 i/o p03 serial data input input -c serial data bus i/o int4 input p00 edge detection vectored interrupt input input (valid for detecting both rising and falling edges) int0 input p10 edge detection vectored interrupt input noise elimination input -c (detected edge is selectable) circuit int0/p10 can select noise elimination /asynchronous circuit. is selectable int1 p11 asynchronous int2 input p12 rising edge detection test input asynchonous input -c kr0 to kr3 input p60 to p63 parallel falling edge detection test input input -a kr4 to kr7 input p70 to p73 parallel falling edge detection test input input -a x1 input ceramic/crystal oscillation circuit connection for main system clock. if using an external clock, input to x1 and input x2 inverted phase to x2. xt1 input crystal oscillation circuit connection for subsystem clock. if using an external clock, input to xt1 and input inverted xt2 phase to xt2. xt1 can be used as a 1-bit (test) input. reset input system reset input (low level active) md0 i/o p30/lcdcl mode selection for program memory (prom) write/verify input e-b md1 p31/sync md2, md3 p32, p33 d0 to d3 i/o p40 to p43 data bus for program memory (prom) write/verify input m-e d4 to d7 p50 to p53 v pp programmable power supply voltage for program memory (prom) write/verify. for normal operation, connect to v dd . apply +12.5 v for prom write/verify. v dd positive power supply v ss ground note circuit types enclosed in brackets indicate schmitt trigger input.
10 m pd75p3036 3.2 non-port pins (2/2) pin name i/o alternate function status i/o circuit function after reset type s12 to s23 output segment signal output note 1 g-a s24 to s31 output bp0 to bp7 segment signal output note 1 h-a com0 to com3 output common signal output note 1 g-b v lc0 to v lc2 power source for lcd driver bias output output for external split resistor cut high impedance lcdcl note 2 output p30/md0 clock output for driving external expansion driver input e-b sync note 2 output p31/md1 clock output for synchronization of external expansion driver input e-b an0 to an5 input analog signal input for a/d converter input y an6 p82 y-b an7 p83 av ref a/d converter reference voltage z-n av ss a/d converter reference gnd potential z-n notes 1. the v lcx (x = 0, 1, 2) shown below are selected as the input source for the display outputs. s12 to s31: v lc1 , com0 to com2: v lc2 , com3: v lc0 2. these pins are provided for future system expansion. currently, only p30 and p31 are used.
m pd75p3036 11 3.3 pin input/output circuits the input/output circuits for the m pd75p3036s pins are shown in schematic form below. in v dd p-ch n-ch v dd p-ch n-ch out data output disable in v dd p-ch in/out p.u.r. enable data p.u.r. type d output disable p.u.r. : pull-up resistor type a v dd p-ch p.u.r. enable p.u.r. p.u.r. : pull-up resistor in p.u.r. : pull-up resistor cmos standard input buffer push-pull output that can be set to output high-impedance (with both p-ch and n-ch off). schmitt trigger input with hysteresis characteristics. type a type d type e-b type b type b-c type e-e v dd p-ch in/out p.u.r. enable data p.u.r. type d output disable type a type b (1/3)
12 m pd75p3036 v dd p-ch in/out p.u.r. enable data p.u.r. type d output disable type b type f-a type g-b type h-a type f-b type g-a type m-c output disable v dd p-ch n-ch in/out data v dd p-ch p.u.r. enable p.u.r. output disable (n) output disable (p) p.u.r. : pull-up resistor in/out type g-a type e-b seg data output disable bit port data n-ch n-ch v lc0 v lc1 seg data v lc2 p-ch out n-ch v lc0 v lc1 com or seg data v lc2 n-ch n-ch p-ch out n-ch p-ch p.u.r. : pull-up resistor (2/3) v dd p-ch in/out p.u.r. enable data p.u.r. output disable p.u.r. : pull-up resistor n-ch * * *
m pd75p3036 13 note becomes active when an input instruction is executed. type m-e type y-b type z-n type y n-ch input enable p-ch in v dd reference voltage av ref v dd p-ch n-ch aden in/out p.u.r. enable data type d output disable type a p.u.r. : pull-up resistor port input note type y v dd av ss sam- pling c reference voltage (from voltage tap of series resistor string) av ss + av ss (3/3) in/out data output disable n-ch p-ch input instruction (+13 v withstand voltage) the pull-up resistor operates only when an input instruction is executed (current flows from v dd to the pin when the pin is low). v dd p.u.r. voltage limitation circuit note (+13 v withstand voltage) note * *
14 m pd75p3036 3.4 recommended connection of unused pins pin recommended connection p00/int4 connect to v ss or v dd p01/sck connect to v ss or v dd via a resistor individually p02/so/sb0 p03/si/sb1 connect to v ss p10/int0 to p12/int2 connect to v ss or v dd p13/ti0 p20/pto0 input status : connect to v ss or v dd via a resistor individually. p21/pto1 output status: open p22/pto2/pcl p23/buz p30/lcdcl p31/sync p32, p33 p40 to p43 connect to v ss p50 to p53 p60/kr0 to p63/kr3 input status : connect to v ss or v dd via a resistor individually. p70/kr4 to p73/kr7 output status: open p80/ti1 p81/ti2 p82/an6 p83/an7 s12 to s23 open s24/bp0 to s31/bp7 com0 to com3 v lc0 to v lc2 connect to v ss bias connect to v ss only when v lc0 to v lc2 are all not used. in other cases, leave open. xt1 note connect to v ss or v dd xt2 note open an0 to an5 connect to v ss or v dd v pp connect to v dd directly note when the subsystem clock is not used, set sos.0 to 1 (so as not to use the internal feedback resistor). *
m pd75p3036 15 4. mk i mode and mk ii mode selection function setting a stack bank selection (sbs) register for the m pd75p3036 enables the program memory to be switched between mk i mode and mk ii mode. this function is applicable when using the m pd75p3036 to evaluate the m pd753036. when the sbs bit 3 is set to 1 : sets mk i mode (supports mk i mode for m pd753036) when the sbs bit 3 is set to 0 : sets mk ii mode (supports mk ii mode for m pd753036) 4.1 difference between mk i mode and mk ii mode table 4-1 lists points of difference between the mk i mode and the mk ii mode for the m pd75p3036. table 4-1. difference between mk i mode and mk ii mode item mk i mode mk ii mode program counter pc 13-0 program memory (bytes) 16384 data memory (bits) 768 x 4 stack stack bank selectable via memory banks 0 to 2 no. of stack bytes 2 bytes 3 bytes instruction bra !addr1 instruction not available available calla !addr1 instruction instruction call !addr instruction 3 machine cycles 4 machine cycles execution time callf !faddr instruction 2 machine cycles 3 machine cycles supported mask rom versions when set to mk i mode for m pd753036 when set to mk ii mode for m pd753036 caution the mk ii mode supports a program area exceeding 16 kbytes for the 75x and 75xl series. therefore, this mode is effective for enhancing software compatibility with products exceeding 16 kbytes. when the mk ii mode is selected, the number of stack bytes used during execution of subroutine call instructions increases by one byte per stack compared to the mk i mode. when the call !addr and callf !faddr instructions are used, the machine cycle becomes longer by one machine cycle. therefore, use the mk i mode if the ram efficiency and processing performance are more important than software compatibility. *
16 m pd75p3036 4.2 setting of stack bank selection register (sbs) use the stack bank selection register to switch between mk i mode and mk ii mode. figure 4-1 shows the format for doing this. the stack bank selection register is set using a 4-bit memory manipulation instruction. when using the mk i mode, be sure to initialize the stack bank selection register to 10xxb note at the beginning of the program. when using the mk ii mode, be sure to initialize it to 00xxb note . note set the desired value for xx. figure 4-1. format of stack bank selection register cautions 1. sbs3 is set to 1 after reset input, and consequently the cpu operates in mk i mode. when using instructions for mk ii mode, set sbs3 to 0 and set mk ii mode before using the instructions. 2. when using mk ii mode, execute a subroutine call instruction and an interrupt instruction after reset input and after setting the stack bank selection register. sbs3 sbs2 sbs1 sbs0 f84h address 3 2 1 0 sbs 0 0 1 1 0 1 0 1 symbol stack area specification memory bank 0 memory bank 1 memory bank 2 setting prohibited 0 be sure to enter ? for bit 2. 0 1 mk ii mode mk i mode mode selection specification
m pd75p3036 17 5. differences between m pd75p3036 and m pd753036 the m pd75p3036 replaces the internal mask rom in the program memory of the m pd753036 with a one-time prom or eprom. the m pd75p3036s mk i mode supports the mk i mode in the m pd753036 and the m pd75p3036s mk ii mode supports the mk ii mode in the m pd753036. table 5-1 lists differences among the m pd75p3036 and the m pd753036. be sure to check the differences among these products before using them with proms for debugging or prototype testing of application systems or, later, when using them with a mask rom for full-scale production. as to cpu function and on-chip hardware, see the users manual . table 5-1. differences between m pd75p3036 and m pd753036 item m pd753036 m pd75p3036 program counter 14 bits program memory (bytes) 16384 16384 mask rom one-time prom, eprom data memory (x 4 bits) 768 mask option pull-up resistor of yes (can specify whether to incorporate no (dont incorporate on-chip) ports 4, 5 on-chip or not) split resistor for lcd driving power supply selection of yes (can select either 2 17 /f x or 2 15 /f x ) note no (fixed to 2 15 /f x ) note oscillation stabilization wait time selection of yes (can select either use enabled or use no (use enabled) subsystem clock disabled) feedback resistor pin configuration pin no. 29 to 32 p40 to p43 p40/d0 to p43/d3 pin no. 34 to 37 p50 to p53 p50/d4 to p53/d7 pin no. 50 p30/lcdcl p30/lcdcl/md0 pin no. 51 p31/sync p31/sync/md1 pin no. 52 p32 p32/md2 pin no. 53 p33 p33/md3 pin no. 69 ic v pp other noise resistance and noise radiation may differ due to the different circuit sizes and mask layouts. note 2 17 /f x is 21.8 ms during 6.0-mhz operation, and 31.3 ms during 4.19-mhz operation. 2 15 /f x is 5.46 ms during 6.0-mhz operation, and 7.81 ms during 4.19-mhz operation. caution noise resistance and noise radiation are different in prom and mask rom versions. in transferring to mask rom versions from the prom version in a process between prototype development and full production, be sure to fully evaluate the mask rom versions cs (not es).
18 m pd75p3036 6.2 program memory (prom) ... 16384 x 8 bits the program memory consists of 16384 x 8-bit one-time prom or eprom. ? addresses 0000h and 0001h vector table wherein the program start address and the values set for the rbe and mbe at the time a reset signal is generated are written. reset start is possible from any address. ? addresses 0002h to 000dh vector table wherein the program start address and the values set for the rbe and mbe by each vectored interrupt are written. interrupt processing can start from any address. ? addresses 0020h to 007fh table area referenced by the geti instruction note . note the geti instruction realizes a 1-byte instruction on behalf of any 2-byte/3-byte instruction, or two 1-byte instructions. it is used to decrease the number of program steps. 6. program counter (pc) and memory map 6.1 program counter (pc) ... 14 bits this is a 14-bit binary counter that stores program memory address data. figure 6-1. configuration of program counter pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 pc
m pd75p3036 19 figure 6-2 shows the addressing ranges for the program memory, branch instruction and the subroutine call instruction. figure 6-2. program memory map note can be used only in the mk ii mode. remark for instructions other than those noted above, the br pcde and br pcxa instructions can be used to branch to addresses with changes in the pcs lower 8 bits only. mbe mbe mbe mbe mbe mbe mbe rbe rbe rbe rbe rbe rbe rbe internal reset start address (upper 6 bits) internal reset start address (lower 8 bits) intbt/int4 start address (upper 6 bits) intbt/int4 start address (lower 8 bits) int0 start address (upper 6 bits) int0 start address (lower 8 bits) int1 start address (upper 6 bits) int1 start address (lower 8 bits) intcsi start address (upper 6 bits) intcsi start address (lower 8 bits) intt0 start address (upper 6 bits) intt0 start address (lower 8 bits) intt1, intt2 start address (upper 6 bits) intt1, intt2 start address (lower 8 bits) reference table for geti instruction 0000h 0002h 0004h 0006h 0008h 000ah 000ch 007fh 0080h 07ffh 0800h 0fffh 1000h 1fffh 2000h 2fffh 3000h 3fffh callf !faddr instruction entry address call !addr instruction subroutine entry address branch/call address by geti br $addr instruction relative branch address (?5 to ?, +2 to +16) brcb !caddr instruction branch address brcb !caddr instruction branch address brcb !caddr instruction branch address brcb !caddr instruction branch address 765 0 0020h branch address for the following instructions ?br bcxa ?br bcde ?br !addr ?bra !addr1 ?calla !addr1 note note *
20 m pd75p3036 6.3 data memory (ram) ... 768 x 4 bits figure 6-3 shows the data memory configuration. data memory consists of a data area and a peripheral hardware area. the data area consists of 768 x 4-bit static ram. figure 6-3. data memory map note memory bank 0, 1, or 2 can be selected as the stack area. (32 x 4) 256 x 4 (224 x 4) 256 x 4 (236 x 4) (20 x 4) 256 x 4 128 x 4 0 1 2 15 000h 01fh 020h 0ffh 100h 1ebh 1ech 1ffh 200h 2ffh f80h fffh general-purpose register area display data memory data area static ram (768 x 4) stack area note peripheral hardware area data memory memory bank not incorporated
m pd75p3036 21 7. instruction set (1) representation and coding formats for operands in the instructions operand area, use the following coding format to describe operands corresponding to the instructions operand representations (for further description, see the ra75x assembler package users manuallanguage (eeu-1363) ). when there are several codes, select and use just one. codes that consist of uppercase letters and + or C symbols are key words that should be entered as they are. for immediate data, enter an appropriate numerical value or label. enter register flag symbols as label descriptors instead of mem, fmem, pmem, bit, etc. (for further description, see the users manual ). the number of labels that can be entered for fmem and pmem are restricted. representation coding format reg x, a, b, c, d, e, h, l reg1 x, b, c, d, e, h, l rp xa, bc, de, hl rp1 bc, de, hl rp2 bc, de rp xa, bc, de, hl, xa, bc, de, hl rp1 bc, de, hl, xa, bc, de, hl rpa hl, hl+, hlC, de, dl rpa1 de, dl n4 4-bit immediate data or label n8 8-bit immediate data or label mem 8-bit immediate data or label note bit 2-bit immediate data or label fmem fb0h-fbfh, ff0h-fffh immediate data or label pmem fc0h-fffh immediate data or label addr 0000h-3fffh immediate data or label addr1 0000h-3fffh immediate data or label caddr 12-bit immediate data or label faddr 11-bit immediate data or label taddr 20h-7fh immediate data (however, bit0 = 0) or label portn port0-port8 iexxx iebt, iecsi, iet0-iet2, ie0-ie2, ie4, iew rbn rb0-rb3 mbn mb0-mb2, mb15 note when processing 8-bit data, only even-numbered addresses can be entered.
22 m pd75p3036 (2) operation legend a : a register; 4-bit accumulator b : b register c : c register d : d register e : e register h : h register l : l register x : x register xa : register pair (xa); 8-bit accumulator bc : register pair (bc) de : register pair (de) hl : register pair (hl) xa : expansion register pair (xa) bc : expansion register pair (bc) de : expansion register pair (de) hl : expansion register pair (hl) pc : program counter sp : stack pointer cy : carry flag; bit accumulator psw : program status word mbe : memory bank enable flag rbe : register bank enable flag portn : port n (n = 0 to 8) ime : interrupt master enable flag ips : interrupt priority selection register iexxx : interrupt enable flag rbs : register bank selection register mbs : memory bank selection register pcc : processor clock control register . : delimiter for address and bit (xx) : the contents addressed by xx xxh : hexadecimal data
m pd75p3036 23 (3) description of symbols used in addressing area remarks 1. mb indicates access-enabled memory banks. 2. in area *2, mb = 0 for both mbe and mbs. 3. in areas *4 and *5, mb = 15 for both mbe and mbs. 4. areas *6 to *11 indicate corresponding address-enabled areas. (4) description of machine cycles s indicates the number of machine cycles required for skipping of skip-specified instructions. the value of s varies as shown below. ? no skip ..................................................................... s = 0 ? skipped instruction is 1-byte or 2-byte instruction .... s = 1 ? skipped instruction is 3-byte instruction note .............. s = 2 note 3-byte instructions: br !addr, bra !addr1, call !addr, calla !addr1 caution the geti instruction is skipped for one machine cycle. one machine cycle equals one cycle (= t cy ) of the cpu clock f . use the pcc setting to select among four cycle times. mb = 0 (000h-07fh) mb = 15 (f80h-fffh) mb = mbs mbs = 0-2, 15 mb = mbe ?mbs mbs = 0-2, 15 *1 mb = 0 *2 mbe = 1 : mbe = 0 : *3 mb = 15, fmem = fb0h-fbfh, ff0h-fffh mb = 15, pmem = fc0h-fffh addr = 0000h-3fffh *4 *5 *6 addr, addr1 = *7 (current pc) ?5 to (current pc) ? (current pc) +2 to (current pc) +16 *8 caddr = 0000h-0fffh (pc 13, 12 = 00b: mk i or mk ii mode) or 1000h-1fffh (pc 13, 12 = 01b: mk i or mk ii mode) or 2000h-2fffh (pc 13, 12 = 10b: mk i or mk ii mode) or 3000h-3fffh (pc 13, 12 = 11b: mk i or mk ii mode) faddr = 0000h-07ffh taddr = 0020h-007fh addr1 = 0000h-3fffh *9 *10 *11 program memory addressing data memory addressing
24 m pd75p3036 instruction mnemonic operand no. of machine operation addressing skip group bytes cycle area condition transfer mov a, #n4 1 1 a<-n4 string-effect a reg1, #n4 2 2 reg1<-n4 xa, #n8 2 2 xa<-n8 string-effect a hl, #n8 2 2 hl<-n8 string-effect b rp2, #n8 2 2 rp2<-n8 a, @hl 1 1 a<-(hl) *1 a, @hl+ 1 2+s a<-(hl), then l<-l+1 *1 l=0 a, @hlC 1 2+s a<-(hl), then l<-lC1 *1 l=fh a, @rpa1 1 1 a<-(rpa1) *2 xa, @hl 2 2 xa<-(hl) *1 @hl, a 1 1 (hl)<-a *1 @hl, xa 2 2 (hl)<-xa *1 a, mem 2 2 a<-(mem) *3 xa, mem 2 2 xa<-(mem) *3 mem, a 2 2 (mem)<-a *3 mem, xa 2 2 (mem)<-xa *3 a, reg1 2 2 a<-reg1 xa, rp 2 2 xa<-rp reg1, a 2 2 reg1<-a rp1, xa 2 2 rp1<-xa xch a, @hl 1 1 a<->(hl) *1 a, @hl+ 1 2+s a<->(hl), then l<-l+1 *1 l=0 a, @hlC 1 2+s a<->(hl), then l<-lC1 *1 l=fh a, @rpa1 1 1 a<->(rpa1) *2 xa, @hl 2 2 xa<->(hl) *1 a, mem 2 2 a<->(mem) *3 xa, mem 2 2 xa<->(mem) *3 a, reg1 1 1 a<->reg1 xa, rp 2 2 xa<->rp table movt xa, @pcde 1 3 xa<-(pc 13-8 +de) rom reference xa, @pcxa 1 3 xa<-(pc 13-8 +xa) rom xa, @bcde 1 3 xa<-(bcde) rom note *6 xa, @bcxa 1 3 xa<-(bcxa) rom note *6 note only the lower 2 bits in the b register are valid.
m pd75p3036 25 instruction mnemonic operand no. of machine operation addressing skip group bytes cycle area condition bit transfer mov1 cy, fmem.bit 2 2 cy<-(fmem.bit) *4 cy, pmem.@l 2 2 cy<-(pmem 7-2 +l 3-2 .bit(l 1-0 )) *5 cy, @h+mem.bit 2 2 cy<-(h+mem 3-0 .bit) *1 fmem.bit, cy 2 2 (fmem.bit)<-cy *4 pmem.@l, cy 2 2 (pmem 7-2 +l 3-2 .bit(l 1-0 ))<-cy *5 @h+mem.bit, cy 2 2 (h+mem 3-0 .bit)<-cy *1 arithmetic/ adds a, #n4 1 1+s a<-a+n4 carry logical xa, #n8 2 2+s xa<-xa+n8 carry operation a, @hl 1 1+s a<-a+(hl) *1 carry xa, rp 2 2+s xa<-xa+rp carry rp1, xa 2 2+s rp1<-rp1+xa carry addc a, @hl 1 1 a, cy<-a+(hl)+cy *1 xa, rp 2 2 xa, cy<-xa+rp+cy rp1, xa 2 2 rp1, cy<-rp1+xa+cy subs a, @hl 1 1+s a<-aC(hl) *1 borrow xa, rp 2 2+s xa<-xaCrp borrow rp1, xa 2 2+s rp1<-rp1Cxa borrow subc a, @hl 1 1 a, cy<-aC(hl)Ccy *1 xa, rp 2 2 xa, cy<-xaCrpCcy rp1, xa 2 2 rp1, cy<-rp1CxaCcy and a, #n4 2 2 a<-a ^ n4 a, @hl 1 1 a<-a ^ (hl) *1 xa, rp 2 2 xa<-xa ^ rp rp1, xa 2 2 rp1<-rp1 ^ xa or a, #n4 2 2 a<-avn4 a, @hl 1 1 a<-av(hl) *1 xa, rp 2 2 xa<-xavrp rp1, xa 2 2 rp1<-rp1vxa xor a, #n4 2 2 a<-av n4 a, @hl 1 1 a<-av (hl) *1 xa, rp 2 2 xa<-xav rp rp1, xa 2 2 rp1<-rp1v xa accumulator rorc a 1 1 cy<-a 0 , a 3 <-cy, a nC1 <-a n manipulation not a 2 2 a<-a increment/ incs reg 1 1+s reg<-reg+1 reg=0 decrement rp1 1 1+s rp1<-rp1+1 rp1=00h @hl 2 2+s (hl)<-(hl)+1 *1 (hl)=0 mem 2 2+s (mem)<-(mem)+1 *3 (mem)=0 decs reg 1 1+s reg<-regC1 reg=fh rp 2 2+s rp<-rpC1 rp=ffh
26 m pd75p3036 instruction mnemonic operand no. of machine operation addressing skip group bytes cycle area condition comparison ske reg, #n4 2 2+s skip if reg=n4 reg=n4 @hl, #n4 2 2+s skip if(hl)=n4 *1 (hl)=n4 a, @hl 1 1+s skip if a=(hl) *1 a=(hl) xa, @hl 2 2+s skip if xa=(hl) *1 xa=(hl) a, reg 2 2+s skip if a=reg a=reg xa, rp 2 2+s skip if xa=rp xa=rp carry flag set1 cy 1 1 cy<-1 manipulation clr1 cy 1 1 cy<-0 skt cy 1 1+s skip if cy=1 cy=1 not1 cy 1 1 cy<-cy memory bit set1 mem.bit 2 2 (mem.bit)<-1 *3 manipulation fmem.bit 2 2 (fmem.bit)<-1 *4 pmem.@l 2 2 (pmem 7-2 +l 3-2 .bit(l 1-0 ))<-1 *5 @h+mem.bit 2 2 (h+mem 3-0 .bit)<-1 *1 clr1 mem.bit 2 2 (mem.bit)<-0 *3 fmem.bit 2 2 (fmem.bit)<-0 *4 pmem.@l 2 2 (pmem 7-2 +l 3-2 .bit(l 1-0 ))<-0 *5 @h+mem.bit 2 2 (h+mem 3-0 .bit)<-0 *1 skt mem.bit 2 2+s skip if(mem.bit)=1 *3 (mem.bit)=1 fmem.bit 2 2+s skip if(fmem.bit)=1 *4 (fmem.bit)=1 pmem.@l 2 2+s skip if(pmem 7-2 +l 3-2 .bit(l 1-0 ))=1 *5 (pmem.@l)=1 @h+mem.bit 2 2+s skip if(h+mem 3-0 .bit)=1 *1 (@h+mem.bit)=1 skf mem.bit 2 2+s skip if(mem.bit)=0 *3 (mem.bit)=0 fmem.bit 2 2+s skip if(fmem.bit)=0 *4 (fmem.bit)=0 pmem.@l 2 2+s skip if(pmem 7-2 +l 3-2 .bit(l 1-0 ))=0 *5 (pmem.@l)=0 @h+mem.bit 2 2+s skip if(h+mem 3-0 .bit)=0 *1 (@h+mem.bit)=0 sktclr fmem.bit 2 2+s skip if(fmem.bit)=1 and clear *4 (fmem.bit)=1 pmem.@l 2 2+s skip if(pmem 7-2 +l 3-2 .bit (l 1-0 ))=1 and clear *5 (pmem.@l)=1 @h+mem.bit 2 2+s skip if(h+mem 3-0 .bit)=1 and clear *1 (@h+mem.bit)=1 and1 cy, fmem.bit 2 2 cy<-cy ^ (fmem.bit) *4 cy, pmem.@l 2 2 cy<-cy ^ (pmem 7-2 +l 3-2 .bit(l 1-0 )) *5 cy, @h+mem.bit 2 2 cy<-cy ^ (h+mem 3-0 .bit) *1 or1 cy, fmem.bit 2 2 cy<-cyv(fmem.bit) *4 cy, pmem.@l 2 2 cy<-cyv(pmem 7-2 +l 3-2 .bit(l 1-0 )) *5 cy, @h+mem.bit 2 2 cy<-cyv(h+mem 3-0 .bit) *1 xor1 cy, fmem.bit 2 2 cy<-cyv (fmem.bit) *4 cy, pmem.@l 2 2 cy<- cyv (pmem 7-2 +l 3-2 .bit(l 1-0 )) *5 cy, @h+mem.bit 2 2 cy<-cyv (h+mem 3-0 .bit) *1
m pd75p3036 27 instruction mnemonic operand no. of machine operation addressing skip group bytes cycle area condition branch br note 1 addr pc 13-0 <-addr *6 use the assembler to select the most appropriate instruction among the following. ? br !addr ? brcb !caddr ? br $addr addr1 pc 13-0 <-addr1 *11 use the assembler to select the most appropriate instruction among the following. ? bra !addr1 ? br !addr ? brcb !caddr ? br $addr1 !addr 3 3 pc 13-0 <-addr *6 $addr 1 2 pc 13-0 <-addr *7 $addr1 1 2 pc 13-0 <-addr1 pcde 2 3 pc 13-0 <-pc 13-8 +de pcxa 2 3 pc 13-0 <-pc 13-8 +xa bcde 2 3 pc 13-0 <-bcde note 2 *6 bcxa 2 3 pc 13-0 <-bcxa note 2 *6 bra note 1 !addr1 3 3 pc 13-0 <-addr1 *11 brcb !caddr 2 2 pc 13-0 <-pc 13, 12 +caddr 11-0 *8 notes 1. the above operations in the double boxes can be performed only in the mk ii mode. the other operations can be performed only in the mk i mode. 2. only the lower 2 bits in the b register are valid.
28 m pd75p3036 instruction mnemonic operand no. of machine operation addressing skip group bytes cycle area condition subroutine calla note !addr1 3 3 (spC6)(spC3)(spC4)<-pc 11-0 *11 stack control (spC5)<-0, 0, pc 13, 12 (spC2)<-x, x, mbe, rbe pc 13C0 <-addr1, sp<-spC6 call note !addr 3 3 (spC4)(spC1)(spC2)<-pc 11-0 *6 (spC3)<-mbe, rbe, pc 13, 12 pc 13C0 <-addr, sp<-spC4 4 (spC6)(spC3)(spC4)<-pc 11-0 (spC5)<-0, 0, pc 13, 12 (spC2)<-x, x, mbe, rbe pc 13-0 <-addr, sp<-spC6 callf note !faddr 2 2 (spC4)(spC1)(spC2)<-pc 11-0 *9 (spC3)<-mbe, rbe, pc 13, 12 pc 13-0 <-000+faddr, sp<-spC4 3 (spC6)(spC3)(spC4)<-pc 11-0 (spC5)<-0, 0, pc 13, 12 (spC2)<-x, x, mbe, rbe pc 13-0 <-000+faddr, sp<-spC6 ret note 1 3 mbe, rbe, pc 13, 12 <-(sp+1) pc 11-0 <-(sp)(sp+3)(sp+2) sp<-sp+4 x, x, mbe, rbe<-(sp+4) pc 11-0 <-(sp)(sp+3)(sp+2) 0, 0, pc 13, 12 <-(sp+1) sp<-sp+6 rets note 1 3+s mbe, rbe, pc 13, 12 <-(sp+1) unconditional pc 11-0 <-(sp)(sp+3)(sp+2) sp<-sp+4 then skip unconditionally x, x, mbe, rbe<-(sp+4) pc 11-0 <-(sp)(sp+3)(sp+2) 0, 0, pc 13, 12 <-(sp+1) sp<-sp+6 then skip unconditionally reti note 1 3 mbe, rbe, pc 13, 12 <-(sp+1) pc 11-0 <-(sp)(sp+3)(sp+2) psw<-(sp+4)(sp+5), sp<-sp+6 0, 0, pc 13, 12 <-(sp+1) pc 11-0 <-(sp)(sp+3)(sp+2) psw<-(sp+4)(sp+5), sp<-sp+6 note the above operations in the double boxes can be performed only in the mk ii mode. the other operations can be performed only in the mk i mode.
m pd75p3036 29 instruction mnemonic operand no. of machine operation addressing skip group bytes cycle area condition subroutine push rp 1 1 (spC1)(spC2)<-rp, sp<-spC2 stack control bs 2 2 (spC1)<-mbs, (spC2)<-rbs, sp<-spC2 pop rp 1 1 rp<-(sp+1)(sp), sp<-sp+2 bs 2 2 mbs<-(sp+1), rbs<-(sp), sp<-sp+2 interrupt ei 2 2 ime(ips.3)<-1 control iexxx 2 2 iexxx<-1 di 2 2 ime(ips.3)<-0 iexxx 2 2 iexxx<-0 i/o in note 1 a, portn 2 2 a<-portn (n=0-8) xa, portn 2 2 xa<-portn+ 1 , portn (n=4, 6) out note 1 portn, a 2 2 portn<-a (n=2-8) portn, xa 2 2 portn+ 1 , portn<-xa (n=4, 6) cpu control halt 2 2 set halt mode(pcc.2<-1) stop 2 2 set stop mode(pcc.3<-1) *10 nop 1 1 no operation special sel rbn 2 2 rbs<-n (n=0-3) mbn 2 2 mbs<-n (n=0-2, 15) geti note 2, 3 taddr 1 3 ? when using tbr instruction pc 13-0 <-(taddr) 5-0 +(taddr+1) ? when using tcall instruction (spC4)(spC1)(spC2)<-pc 11-0 (spC3)<-mbe, rbe, pc 13, 12 pc 13-0 <-(taddr) 5-0 +(taddr+1) sp<-spC4 ? when using instruction other than determined by tbr or tcall referenced execute (taddr)(taddr+1) instruction instruction 1 3 ? when using tbr instruction *10 pc 13-0 <-(taddr) 5-0 +(taddr+1) 4 ? when using tcall instruction (spC6)(spC3)(spC4)<-pc 11-0 (spC5)<-mbe, rbe, pc 13, 12 (spC2)<-x, x, mbe, rbe pc 13-0 <-(taddr) 5-0 +(taddr+1) sp<-spC6 3 ? when using instruction other than determined by tbr or tcall referenced execute (taddr)(taddr+1) instruction instruction notes 1. before executing the in or out instruction, set mbe to 0 or 1 and set mbs to 15. 2. tbr and tcall instructions are assembler pseudo-instructions for the geti instructions table definitions. 3. the above operations in the double boxes can be performed only in the mk ii mode. the other operations can be performed only in the mk i mode. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
30 m pd75p3036 8. prom (program memory) write and verify the m pd75p3036 contains a 16384 x 8-bit prom as a program memory. the pins listed in the table below are used for this proms write/verify operations. clock input from the x1 pin is used instead of address input as a method for updating addresses. pin function v pp pin where program voltage is applied during program memory write/verify (usually v dd potential) x1, x2 clock input pins for address updating during program memory write/verify. input the x1 pins inverted signal to the x2 pin. md0 to md3 operation mode selection pin for program memory write/verify d0/p40 to d3/p43 8-bit data i/o pins for program memory write/verify (lower 4 bits) d4/p50 to d7/p53 (upper 4 bits) v dd pin where power supply voltage is applied. applies 1.8 to 5.5 v in normal operation mode and +6 v for program memory write/verify. caution pins not used for program memory write/verify should be connected to v ss . 8.1 operation modes for program memory write/verify when +6 v is applied to the v dd pin and +12.5 v to the v pp pin, the m pd75p3036 enters the program memory write/verify mode. the following operation modes can be specified by setting pins md0 to md3 as shown below. operation mode specification operation mode v pp v dd md0 md1 md2 md3 +12.5 v +6 v h l h l zero-clear program memory address l h h h write mode l l h h verify mode h x h h program inhibit mode x: l or h
m pd75p3036 31 8.2 program memory write procedure program memory can be written at high speed using the following procedure. (1) pull unused pins to v ss through resistors. set the x1 pin low. (2) supply 5 v to the v dd and v pp pins. (3) wait 10 m s. (4) select the zero-clear program memory address mode. (5) supply 6 v to the v dd and 12.5 v to the v pp pins. (6) write data in the 1 ms write mode. (7) select the verify mode. if the data is correct, go to step (8) and if not, repeat steps (6) and (7). (8) (x : number of write operations from steps (6) and (7)) x 1 ms additional write. (9) apply four pulses to the x1 pin to increment the program memory address by one. (10) repeat steps (6) to (9) until the end address is reached. (11) select the zero-clear program memory address mode. (12) return the v dd and v pp pins back to 5 v. (13) turn off the power. the following figure shows steps (2) to (9). v pp v dd v dd + 1 v dd v pp v dd x1 d0/p40-d3/p43 d4/p50-d7/p53 md0/p30 md1/p31 md2/p32 md3/p33 data input data output data input x repetitions write verify additional write address increment *
32 m pd75p3036 8.3 program memory read procedure the m pd75p3036 can read program memory contents using the following procedure. (1) pull unused pins to v ss through resistors. set the x1 pin low. (2) supply 5 v to the v dd and v pp pins. (3) wait 10 m s. (4) select the zero-clear program memory address mode. (5) supply 6 v to the v dd and 12.5 v to the v pp pins. (6) select the verify mode. apply four clock pulses to the x1 pin. every four clock pulses will output the data stored in one address. (7) select the zero-clear program memory address mode. (8) return the v dd and v pp pins back to 5 v. (9) turn off the power. the following figure shows steps (2) to (7). v pp v dd v dd + 1 v dd v pp v dd x1 d0/p40-d3/p43 d4/p50-d7/p53 md0/p30 md2/p32 md3/p33 md1/p31 ? data output data output *
m pd75p3036 33 9. program erasure ( m pd75p3036kk-t only) the m pd75p3036kk-t is capable of erasing (ffh) the data written in a program memory and rewriting. to erase the programmed data, expose the erasure window to light having a wavelength shorter than about 400 nm. normally, irradiate ultraviolet rays of 254-nm wavelength. the amount of exposure required to completely erase the programmed data is as follows: ? uv intensity x erasure time : 15 w? s/cm 2 or more ? erasure time : 15 to 20 minutes (when a uv lamp of 12000 m w/cm 2 is used. however, a longer time may be needed because of deterioration in performance of the uv lamp, soiled erasure window, etc.) when erasing the contents of data, set up the uv lamp within 2.5 cm from the erasure window. further, if a filter is provided for a uv lamp, irrradiate the ultraviolet rays after removing the filter. 10. opaque film on erasure window ( m pd75p3036kk-t only) to protect from unintentional erasure by rays other than that of the lamp for erasing eprom contents, and to protect internal circuit other than eprom from misoperating due to light radiation, cover the erasure window with an opaque film when eprom contents erasure is not performed. 11. one-time prom screening due to its structure, the one-time prom versions ( m pd75p3036gc-3b9, m pd75p3036gk-be9) cannot be fully tested before shipment by nec. therefore, nec recommends that after the required data is written and the prom is stored under the temperature and time conditions shown below, the prom should be verified via a screening. storage temperature storage time 125 ?c 24 hours * *
34 m pd75p3036 12. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd C0.3 to +7.0 v prom supply voltage v pp C0.3 to +13.5 v input voltage v i1 other than ports 4, 5 C0.3 to v dd +0.3 v v i2 ports 4, 5 n-ch open drain C0.3 to +14 v output voltage v o C0.3 to v dd +0.3 v high-level output current i oh per pin C10 ma total of all pins C30 ma low-level output current i ol per pin 30 ma total of all pins 200 ma operating ambient t a C40 to +85 note ?c temperature storage temperature t stg C65 to +150 ?c note to drive lcd at 1.8 v v dd < 2.7 v, t a = C10 to +85 c caution if the absolute maximum ratings of even one of the parameters is exceeded even momentarily, the quality of the product may be degraded. the absolute maximum ratings are therefore values which, when exceeded, can cause the product to be damaged. be sure that these values are never exceeded when using the product. capacitance (t a = 25 c, v dd = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c in f = 1 mhz 15 pf output capacitance c out unmeasured pins returned to 0 v 15 pf i/o capacitance c io 15 pf *
m pd75p3036 35 main system clock oscillation circuit characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended parameter conditions min. typ. max. unit constants ceramic oscillation frequency 1.0 6.0 note 2 mhz resonator (f x ) note 1 oscillation after v dd has 4 ms stabilization time note 3 reached min. value of oscillation voltage range crystal oscillation frequency 1.0 6.0 note 2 mhz resonator (f x ) note 1 oscillation v dd = 4.5 to 5.5 v 10 ms stabilization time note 3 30 external x1 input frequency 1.0 6.0 note 2 mhz clock (f x ) note 1 x1 input high-, 83.3 500 ns low-level widths (t xh , t xl ) notes 1. the oscillation frequency and x1 input frequency shown above indicate characteristics of the oscillation circuit only. for the instruction execution time, refer to ac characteristics. 2. if the oscillation frequency is 4.19 mhz < f x 6.0 mhz at 1.8 v v dd < 2.7 v, do not select the processor clock control register (pcc) = 0011. if pcc = 0011, one machine cycle time is less than 0.95 m s, falling short of the rated value of 0.95 m s. 3. the oscillation stabilization time is the time required for oscillation to be stabilized after v dd has been applied or stop mode has been released. caution when using the main system clock oscillation circuit, wire the portion enclosed in the dotted line in the above figure as follows to prevent adverse influence due to wiring capacitance: ? keep the wiring length as short as possible. ? do not cross the wiring with other signal lines. ? do not route the wiring in the vicinity of a line through which a high alternating current flows. ? always keep the ground point of the capacitor of the oscillation circuit at the same potential as v dd . ? do not ground to a power supply pattern through which a high current flows. ? do not extract signals from the oscillation circuit. x1 x2 c1 c2 v dd x1 x2 c1 c2 v dd x1 x2
36 m pd75p3036 subsystem clock oscillation circuit characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended parameter conditions min. typ. max. unit constants crystal oscillation frequency 32 32.768 35 khz resonator (f xt ) note 1 oscillation v dd = 4.5 to 5.5 v 1.0 2 s stabilization time note 2 10 external xt1 input frequency 32 100 khz clock (f xt ) note 1 xt1 input high-, 5 15 m s low-level widths (t xth , t xtl ) notes 1. the oscillation frequency shown above indicate characteristics of the oscillation circuit only. for the instruction execution time, refer to ac characteristics. 2. the oscillation stabilization time is the time required for oscillation to be stabilized after v dd has been applied. caution when using the subsystem clock oscillation circuit, wire the portion enclosed in the dotted line in the above figure as follows to prevent adverse influence due to wiring capacitance: ? keep the wiring length as short as possible. ? do not cross the wiring with other signal lines. ? do not route the wiring in the vicinity of a line through which a high alternating current flows. ? always keep the ground point of the capacitor of the oscillation circuit at the same potential as v dd . ? do not ground to a power supply pattern through which a high current flows. ? do not extract signals from the oscillation circuit. the subsystem clock oscillation circuit has a low amplification factor to reduce current dissipation and is more susceptible to noise than the main system clock oscillation circuit. therefore, exercise utmost care in wiring the subsystem clock oscillation circuit. xt1 xt2 c3 c4 v dd r xt1 xt2
m pd75p3036 37 dc characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit low-level output i ol per pin 15 ma current total of all pins 120 ma high-level input v ih1 ports 2, 3, p82, p83 2.7 v v dd 5.5 v 0.7 v dd v dd v voltage 1.8 v v dd < 2.7 v 0.9 v dd v dd v v ih2 ports 0, 1, 6, 7, p80, p81, 2.7 v v dd 5.5 v 0.8 v dd v dd v reset 1.8 v v dd < 2.7 v 0.9 v dd v dd v v ih3 ports 4, 5 n-ch open drain 2.7 v v dd 5.5 v 0.7 v dd 13 v 1.8 v v dd < 2.7 v 0.9 v dd 13 v v ih4 x1, xt1 v dd C0.1 v dd v low-level input v il1 ports 2, 3, 4, 5, p82, p83 2.7 v v dd 5.5 v 0 0.3 v dd v voltage 1.8 v v dd < 2.7 v 0 0.1 v dd v v il2 ports 0, 1, 6, 7, p80, p81, 2.7 v v dd 5.5 v 0 0.2 v dd v reset 1.8 v v dd < 2.7 v 0 0.1 v dd v v il3 x1, xt1 0 0.1 v high-level output v oh sck, so, ports 2, 3, 6, 7, 8, bp0 to bp7 v dd C0.5 v voltage i oh = C1 ma low-level output v ol1 sck, so, ports 2 to 8, i ol = 15 ma 0.2 2.0 v voltage bp0 to bp7 v dd = 4.5 to 5.5 v i ol = 1.6 ma 0.4 v v ol2 sb0, sb1 n-ch open drain 0.2 v dd v pull-up resistor 3 1 k w high-level input i lih1 v in = v dd pins other than x1, xt1 3 m a leakage current i lih2 x1, xt1 20 m a i lih3 v in = 13 v ports 4, 5 (n-ch open drain) 20 m a low-level input i lil1 v in = 0 v pins other than ports 4, 5, x1, xt1 C3 m a leakage current i lil2 x1, xt1 C20 m a ports 4, 5 (n-ch open drain) C3 m a when input instruction is not executed i lil3 C30 m a v dd = 5 v C10 C27 m a v dd = 3 v C3 C8 m a high-level output i loh1 v out = v dd sck, so/sb0, sb1, ports 2, 3, 6, 7, 8, 3 m a leakage current bp0 to bp7 i loh2 v out = 13 v ports 4, 5 (n-ch open drain) 20 m a low-level output i lol v out = 0 v C3 m a leakage current internal pull-up r l1 v in = 0 v ports 0 to 3, 6 to 8 (except pin p00) 50 100 200 k w resistor ports 4, 5 (n-ch open drain) when input instruc- tion is executed
38 m pd75p3036 dc characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit lcd drive voltage v lcd vac0 = 0 C40 to + 85 ?c 2.7 v dd v C10 to + 85 ?c 2.2 v dd v vac0 = 1 1.8 v dd v vac current note 1 i vac vac0 = 1, v dd = 2.0 v 10 % 1 4 m a lcd output voltage v odc i o = 1.0 m a v lcd0 = v lcd 0 0.2 v deviation note 2 v lcd1 = v lcd 2/3 (common) v lcd2 = v lcd 1/3 lcd output voltage v ods i o = 0.5 m a 1.8 v v lcd v dd note 1 0 0.2 v deviation note 2 (segment) supply current notes 1, 3 i dd1 v dd = 5.0 v 10 % note 5 3.5 10.5 ma v dd = 3.0 v 10 % note 6 0.86 2.5 ma i dd2 halt v dd = 5.0 v 10 % 0.9 2.7 ma mode v dd = 3.0 v 10 % 0.5 1.0 ma i dd1 v dd = 5.0 v 10 % note 5 2.7 8.1 ma v dd = 3.0 v 10 % note 6 0.33 1.0 ma i dd2 halt v dd = 5.0 v 10 % 0.7 2.0 ma mode v dd = 3.0 v 10 % 0.3 0.9 ma i dd3 low- v dd = 3.0 v 10 % 45 135 m a voltage v dd = 2.0 v 10 % 22 66 m a mode note 8 v dd = 3.0 v, t a = 25 ?c 45 90 m a v dd = 3.0 v 10 % 43 129 m a v dd = 3.0 v, t a = 25 ?c 43 86 m a i dd4 halt low- v dd = 3.0 v 10 % 8.5 25 m a mode voltage v dd = 2.0 v 10 % 3.0 9.0 m a mode note 8 v dd = 3.0 v, t a = 25 ?c 8.5 17 m a v dd = 3.0 v 10 % 4.6 13.8 m a v dd = 3.0 v, t a = 25 ?c 4.6 9.2 m a i dd5 xt1 = v dd = 5.0 v 10 % 0.05 10 m a 0 v note 10 v dd = 3.0 v 10 % 0.02 5.0 m a stop mode t a = 25 ?c 0.02 3.0 m a notes 1. clear vac0 to 0 in the low current dissipation mode and stop mode. when vac0 is set to 1, the current increases by about 1 m a. 2. voltage deviation is the difference between the ideal values (v lcdn ; n = 0, 1, 2) of the segment and common outputs and the output voltage. 3. the current flowing through the internal pull-up resistor is not included. 4. including the case when the subsystem clock oscillates. 5. when the device operates in high-speed mode with the processor clock control register (pcc) set to 0011. 6. when the device operates in low-speed mode with pcc set to 0000. 7. when the device operates on the subsystem clock, with the system clock control register (scc) set to 1001 and oscillation of the main system clock stopped. 8. when the sub-oscillation circuit control register (sos) is set to 0000. 9. when sos is set to 0010. 10. when sos is set to 00 1, and the feedback resistor of the sub-oscillation circuit is not used ( : don't care). 6.00 mhz note 4 crystal oscillation c1 = c2 = 22 pf 4.19 mhz note 4 crystal oscillation c1 = c2 = 22 pf 32.768 khz note 7 crystal oscillation low current dissipation mode note 9 low current dissipation mode note 9
m pd75p3036 39 ac characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit cpu clock cycle time note 1 t cy operates with v dd = 2.7 to 5.5 v 0.67 64 m s (minimum instruction main system clock 0.95 64 m s execution time = 1 operates with 114 122 125 m s machine cycle) subsystem clock ti0, ti1, ti2 input frequency f ti v dd = 2.7 to 5.5 v 0 1.0 mhz 0 275 khz ti0, ti1, ti2 high-, low-level t tih , t til v dd = 2.7 to 5.5 v 0.48 m s widths 1.8 m s interrupt input high-, t inth , t intl int0 im02 = 0 note 2 m s low-level widths im02 = 1 10 m s int1, 2, 4 10 m s kr0 to kr7 10 m s reset low-level width t rsl 10 m s notes 1. the cycle time of the cpu clock ( f ) is determined by the oscillation frequency of the connected resonator (and ex- ternal clock), the system clock control register (scc), and processor clock control register (pcc). the figure on the right shows the sup- ply voltage v dd vs. cycle time t cy char- acteristics when the device operates with the main system clock. 2. 2t cy or 128/f x depending on the setting of the interrupt mode register (im0). 0 1 2 3 4 5 6 1 0.5 2 3 4 5 6 60 64 (with main system clock) t cy vs v dd operation guaranteed range cycle time t cy [ s] m supply voltage v dd [v]
40 m pd75p3036 serial transfer operation 2-wire and 3-wire serial i/o modes (sck internal clock output): (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit sck cycle time t kcy1 v dd = 2.7 to 5.5 v 1300 ns 3800 ns sck high-, low-level widths t kl1 ,v dd = 2.7 to 5.5 v t kcy1 /2C50 ns t kh1 t kcy1 /2C150 ns si note 1 setup time (to sck - )t sik1 v dd = 2.7 to 5.5 v 150 ns 500 ns si note 1 hold time t ksi1 v dd = 2.7 to 5.5 v 400 ns (from sck - ) 600 ns sck ? so note 1 output t kso1 r l = 1 k w ,v dd = 2.7 to 5.5 v 0 250 ns delay time c l = 100 pf 0 1000 ns notes 1. read as sb0 or sb1 when using the 2-wire serial i/o mode. 2. r l and c l respectively indicate the load resistance and load capacitance of the so output line. 2-wire and 3-wire serial i/o modes (sck external clock input): (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit sck cycle time t kcy2 v dd = 2.7 to 5.5 v 800 ns 3200 ns sck high-, low-level widths t kl2 ,v dd = 2.7 to 5.5 v 400 ns t kh2 1600 ns si note 1 setup time (to sck - )t sik2 v dd = 2.7 to 5.5 v 100 ns 150 ns si note 1 hold time t ksi2 v dd = 2.7 to 5.5 v 400 ns (from sck - ) 600 ns sck ? so note 1 output t kso2 r l = 1 k w ,v dd = 2.7 to 5.5 v 0 300 ns delay time c l = 100 pf 0 1000 ns notes 1. read as sb0 or sb1 when using the 2-wire serial i/o mode. 2. r l and c l respectively indicate the load resistance and load capacitance of the so output line. note 2 note 2
m pd75p3036 41 note sbi mode (sck internal clock output (master)): (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit sck cycle time t kcy3 v dd = 2.7 to 5.5 v 1300 ns 3800 ns sck high-, low-level widths t kl3 ,v dd = 2.7 to 5.5 v t kcy3 /2C50 ns t kh3 t kcy3 /2C150 ns sb0, 1 setup time t sik3 v dd = 2.7 to 5.5 v 150 ns (to sck - ) 500 ns sb0, 1 hold time (from sck - ) t ksi3 t kcy3 /2 ns sck ? sb0, 1 output t kso3 r l = 1 k w ,v dd = 2.7 to 5.5 v 0 250 ns delay time c l = 100 pf 0 1000 ns sck - ? sb0, 1 t ksb t kcy3 ns sb0, 1 ? sck t sbk t kcy3 ns sb0, 1 low-level width t sbl t kcy3 ns sb0, 1 high-level width t sbh t kcy3 ns note r l and c l respectively indicate the load resistance and load capacitance of the sb0, 1 output line. sbi mode (sck external clock input (slave)): (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit sck cycle time t kcy4 v dd = 2.7 to 5.5 v 800 ns 3200 ns sck high-, low-level widths t kl4 ,v dd = 2.7 to 5.5 v 400 ns t kh4 1600 ns sb0, 1 setup time t sik4 v dd = 2.7 to 5.5 v 100 ns (to sck - ) 150 ns sb0, 1 hold time (from sck - ) t ksi4 t kcy4 /2 ns sck ? sb0, 1 output t kso4 r l = 1 k w ,v dd = 2.7 to 5.5 v 0 300 ns delay time c l = 100 pf 0 1000 ns sck - ? sb0, 1 t ksb t kcy4 ns sb0, 1 ? sck t sbk t kcy4 ns sb0, 1 low-level width t sbl t kcy4 ns sb0, 1 high-level width t sbh t kcy4 ns note r l and c l respectively indicate the load resistance and load capacitance of the sb0, 1 output line. note
42 m pd75p3036 a/d converter characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v, 1.8 v av ref v dd ) parameter symbol conditions min. typ. max. unit resolution 888bit absolute accuracy note 1 v dd = av ref 2.7 v v dd 5.5 v 1.5 lsb 1.8 v v dd < 2.7 v 3 lsb v dd 1 av ref 3 lsb conversion time t conv note 2 168/f x m s sampling time t samp note 3 44/f x m s analog input voltage v ian av ss av ref v analog input impedance r an 1000 m w av ref current i ref 0.25 2.0 ma notes 1. absolute accuracy excluding quantization error ( 1/2lsb) 2. time until end of conversion (eoc = 1) after execution of conversion start instruction (40.1 m s: f x = 4.19 mhz). 3. time until end of sampling after execution of conversion start instruction (10.5 m s: f x = 4.19 mhz).
m pd75p3036 43 ac timing test points (except x1 and xt1 inputs) v ih (min.) v il (max.) v ih (min.) v il (max.) v oh (min.) v ol (max.) v oh (min.) v ol (max.) clock timing ti0, ti1, ti2 timing 1/f x t xl t xh v dd ?0.1 v 0.1 v x1 input 1/f xt t xtl t xth v dd ?0.1 v 0.1 v xt1 input 1/f ti t til t tih ti0, ti1, ti2
44 m pd75p3036 serial transfer timing 3-wire serial i/o mode 2-wire serial i/o mode t kcy1, 2 t kl1, 2 t kh1, 2 sck output data so input data si t sik1, 2 t ksi1, 2 t kso1, 2 t kcy1, 2 t kl1, 2 t kh1, 2 sck sb0, 1 t sik1, 2 t ksi1, 2 t kso1, 2
m pd75p3036 45 reset input timing serial transfer timing bus release signal transfer command signal transfer interrupt input timing int0, 1, 2, 4 kr0-7 t intl t inth sck sb0, 1 t kcy3, 4 t sik3, 4 t kso3, 4 t ksi3, 4 t sbk t sbh t sbl t ksb t kh3, 4 t kl3, 4 sck sb0, 1 t kcy3, 4 t sik3, 4 t kso3, 4 t kl3, 4 t kh3, 4 t ksi3, 4 t sbk t ksb reset t rsl
46 m pd75p3036 data retention characteristics of data memory in stop mode and at low supply voltage (t a = C40 to +85 c) parameter symbol conditions min. typ. max. unit release signal setup time t srel 0 m s oscillation stabilization t wait released by reset 2 15 /f x ms wait time note 1 released by interrupt request note 2 ms notes 1. the oscillation stabilization wait time is the time during which the cpu stops operating to prevent unstable operation when oscillation is started. 2. set by the basic interval timer mode register (btm). (refer to the table below.) btm3 btm2 btm1 btm0 wait time f x = 4.19 mhz f x = 6.0 mhz C0002 20 /f x (approx. 250 ms) 2 20 /f x (approx. 175 ms) C0112 17 /f x (approx. 31.3 ms) 2 17 /f x (approx. 21.8 ms) C1012 15 /f x (approx. 7.81 ms) 2 15 /f x (approx. 5.46 ms) C1112 13 /f x (approx. 1.95 ms) 2 13 /f x (approx. 1.37 ms) data retention timing (when stop mode released by reset) data retention timing (standby release signal: when stop mode released by interrupt signal) stop mode data retention mode operation mode oscillation stabilization wait time t srel v dddr t wait stop instruction execution v dd standby release signal (interrupt request) stop mode data retention mode internal reset operation operation mode stop instruction execution oscillation stabilization wait time v dd reset v dddr t wait t srel
m pd75p3036 47 dc programming characteristics (t a = 25 5 ?c, v dd = 6.0 0.25 v, v pp = 12.5 0.3 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit high-level input voltage v ih1 except x1, x2 0.7 v dd v dd v v ih2 x1, x2 v dd C0.5 v dd v low-level input voltage v il1 except x1, x2 0 0.3 v dd v v il2 x1, x2 0 0.4 v input leakage current i li v in = v il or v ih 10 m a high-level output voltage v oh i oh = C1 ma v dd C1.0 v low-level output voltage v ol i ol = 1.6 ma 0.4 v v dd supply current i dd 30 ma v pp supply current i pp md0 = v il , md1 = v ih 30 ma cautions 1. ensure that v pp does not exceed +13.5 v including overshoot. 2. v dd must be applied before v pp , and cut after v pp . ac programming characteristics (t a = 25 5 ?c, v dd = 6.0 0.25 v, v pp = 12.5 0.3 v, v ss = 0 v) parameter symbol note 1 conditions min. typ. max. unit address setup time note 2 (to md0 )t as t as 2 m s md1 setup time (to md0 )t m1s t oes 2 m s data setup time (to md0 )t ds t ds 2 m s address hold time note 2 (from md0 - )t ah t ah 2 m s data hold time (from md0 - )t dh t dh 2 m s md0 -? data output float delay time t df t df 0 130 ns v pp setup time (to md3 - )t vps t vps 2 m s v dd setup time (to md3 - )t vds t vcs 2 m s initial program pulse width t pw t pw 0.95 1.0 1.05 ms additional program pulse width t opw t opw 0.95 21.0 ms md0 setup time (to md1 - )t m0s t ces 2 m s md0 ? data output delay time t dv t dv md0 = md1 = v il 1 m s md1 hold time (from md0 - )t m1h t oeh t m1h + t m1r 3 50 m s2 m s md1 recovery time (from md0 )t m1r t or 2 m s program counter reset time t pcr 10 m s x1 input high-, low-level widths t xh , t xl 0.125 m s x1 input frequency f x 4.19 mhz initial mode setting time t i 2 m s md3 setup time (to md1 - )t m3s 2 m s md3 hold time (from md1 )t m3h 2 m s md3 setup time (to md0 )t m3sr program memory read 2 m s data output delay time from address note 2 t dad t acc program memory read 2 m s data output hold time from address note 2 t had t oh program memory read 0 130 m s md3 hold time (from md0 - )t m3hr program memory read 2 m s md3 ? data output float delay time t dfr program memory read 2 m s notes 1. symbol of corresponding m pd27c256a 2. the internal address signal is incremented by 1 on the 4th rise of the x1 input, and is not connected to a pin.
48 m pd75p3036 program memory write timing program memory read timing v pp v dd v dd +1 v dd x1 d0/p40-d3/p43 d4/p50-d7/p53 md0 md1 md2 md3 v pp v dd data input data output data input data input t vps t vds t xh t xl t i t ds t dh t pw t dv t df t m1r t m0s t ds t dh t opw t ah t as t m1s t m1h t pcr t m3s t m3h v pp v dd v dd +1 v dd x1 d0/p40-d3/p43 d4/p50-d7/p53 md0 md1 md2 md3 v dd v pp data output data output t vps t vds t xh t xl t dad t had t dv t dfr t m3hr t i t pcr t m3sr
m pd75p3036 49 13. characteristic curves (for reference only) i dd vs. v dd (main system clock: 6.0-mhz crystal resonator) 10 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 01234 5678 supply voltage v dd (v) supply current i dd (ma) 22 pf 22 pf 22 pf 22 pf v dd v dd 6.0 mhz 32.768 khz crystal resonator crystal resonator x1 x2 xt1 xt2 330 k subsystem clock operation mode (sos.1 = 0) subsystem clock halt mode (sos.1 = 0) main system clock stop mode + 32 khz oscillation (sos.1 = 0) subsystem clock halt mode (sos.1 = 1) main system clock stop mode + 32 khz oscillation (sos.1 = 1) pcc = 0011 pcc = 0000 pcc = 0010 main system clock halt mode + 32 khz oscillation (t a = 25 c ) pcc = 0001 *
50 m pd75p3036 i dd vs. v dd (main system clock: 4.19-mhz crystal resonator) 10 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 01 23 45 678 pcc = 0010 pcc = 0011 pcc = 0001 pcc = 0000 main system clock halt mode + 32 khz oscillation subsystem clock operation mode (sos.1 = 0) subsystem clock halt mode (sos.1 = 0) main system clock stop mode + 32 khz oscillation (sos.1 = 0) subsystem clock halt mode (sos.1 = 1) main system clock stop mode + 32 khz oscillation (sos.1 = 1) (t a = 25 c) 22 pf 22 pf 22 pf 22 pf v dd v dd 4.19 mhz 32.768 khz crystal resonator crystal resonator x1 x2 xt1 xt2 330 k supply voltage v dd (v) supply current i dd (ma)
m pd75p3036 51 14. package drawings 80 pin plastic qfp (14 14) item millimeters inches note each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. l 0.8?.2 0.031 +0.009 ?.008 m 0.15 0.006 n 0.10 0.004 p 2.7 0.106 a 17.2?.4 0.677?.016 b 14.0?.2 0.551 +0.009 ?.008 c 14.0?.2 0.551 +0.009 ?.008 d 17.2?.4 0.677?.016 f 0.825 0.032 g 0.825 0.032 h 0.30?.10 0.012 +0.004 ?.005 i 0.13 0.005 j 0.65 (t.p.) 0.026 (t.p.) q 0.1?.1 0.004?.004 r5 ? 5 ? +0.10 ?.05 +0.004 ?.003 m m l k j h q p n r detail of lead end i g k 1.6?.2 0.063?.008 60 61 40 80 1 21 20 41 a b cd f s s80gc-65-3b9-4 s 3.0 max. 0.119 max.
52 m pd75p3036 80 pin plastic tqfp (fine pitch) ( 12) item millimeters inches i j 0.5 (t.p.) 0.10 0.004 0.020 (t.p.) a note each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. s a 14.0?.2 0.551 +0.009 ?.008 b 12.0?.2 0.472 +0.009 ?.008 c 12.0?.2 0.472 +0.009 ?.008 d 14.0?.2 0.551 +0.009 ?.008 f g 1.25 1.25 0.049 0.049 h 0.22 0.009?.002 p80gk-50-be9-4 s 1.27 max. 0.050 max. k 1.0?.2 0.039 +0.009 ?.008 l 0.5?.2 0.020 +0.008 ?.009 m 0.145 0.006?.002 n 0.10 0.004 p 1.05 0.041 q 0.05?.05 0.002?.002 r 55? 55? +0.05 ?.04 +0.055 ?.045 b c d j h i g f p n l k m q r detail of lead end m 61 60 41 40 21 20 1 80
m pd75p3036 53 z u1 a t b d c u g f w r s q k m i h j x80kw-65a-1 item millimeters inches a b c d f g h i j k q 14.0 0.2 13.6 3.6 max. 0.06 13.6 0.551 0.008 0.072 0.142 max. 0.003 0.024 (t.p.) 0.535 note r s 0.825 0.825 0.65 (t.p.) 0.032 0.032 each lead centerline is located within 0.06 mm (0.003 inch) of its true position (t.p.) at maximum material condition. 0.018 0.535 t r 2.0 r 0.079 0.551 0.008 14.0 0.2 1.84 u 9.0 0.354 u1 2.1 0.083 +0.004 ?.005 w z 0.10 0.004 80 1 0.45 0.10 0.039 +0.007 ?.006 1.0 0.15 c 0.3 c 0.012 0.75 0.15 0.030 +0.006 ?.007 80 pin ceramic wqfn *
54 m pd75p3036 15. recommended soldering conditions solder the m pd75p3036 under the following recommended conditions. for the details on the recommended soldering conditions, refer to information document semiconductor device mounting technology manual (c10535e) . for the soldering methods and conditions other than those recommended, consult nec. table 15-1. soldering conditions of surface mount type (1) m pd75p3036gc-3b9: 80-pin plastic qfp (14 14 mm) soldering method soldering conditions symbol infrared reflow package peak temperature: 235 ?c, reflow time: 30 seconds or below ir35-00-3 (210 ?c or higher), number of reflow processes: 3 max. vps package peak temperature: 215 ?c, reflow time: 40 seconds or below vp15-00-3 (200 ?c or higher), number of reflow processes: 3 max. wave soldering solder temperature: 260 ?c or below, flow time: 10 seconds or below, ws60-00-1 number of flow processes: 1 preheating temperature: 120 ?c or below (package surface temperature) pin partial heating pin temperature: 300 ?c or below, time: 3 seconds or below (per side of device) caution do not use two or more soldering methods in combination (except the pin partial heating method). (2) m pd75p3036gk-be9: 80-pin plastic tqfp (fine pitch) (12 12 mm) soldering method soldering conditions symbol infrared reflow ir35-107-3 vps vp15-107-3 wave soldering ws60-107-1 pin partial heating note the number of days for storage after the dry pack has been opened. the storage conditions are 25 ?c, 65 % rh max. caution do not use two or more soldering methods in combination (except the pin partial heating method). package peak temperature: 235 ?c, reflow time: 30 seconds or below (210 ?c or higher), number of reflow processes: 3 max., exposure limit: 7 days note (after that, prebaking is necessary at 125 ?c for 10 hours.) package peak temperature: 215 ?c, reflow time: 40 seconds or below (200 ?c or higher), number of reflow processes: 3 max., exposure limit: 7 days note (after that, prebaking is necessary at 125 ?c for 10 hours.) solder temperature: 260 ?c or below, flow time: 10 seconds or below, number of flow processes: 1, preheating temperature: 120 ?c or below (package surface temperature) exposure limit: 7 days note (after that, prebaking is necessary at 125 ?c for 10 hours.) pin temperature: 300 ?c or below, time: 3 seconds or below (per side of device) *
m pd75p3036 55 appendix a. function list of m pd75336, 753036, and 75p3036 m pd75336 m pd753036 m pd75p3036 rom (bytes) 16256 16384 16384 mask rom mask rom one-time prom, eprom ram (x 4 bits) 768 mk i, mk ii mode selection function no yes instruction set 75x high-end 75xl i/o ports total 44 cmos input 8 cmos i/o 20 (4 of which can directly drive leds) cmos output 8 (also used as segment pins) n-ch open-drain i/o 8 (can directly drive leds, medium-voltage port) mask options yes no timers 4 channels: 5 channels: ? 8-bit timer/ ? 8-bit timer/event counters ........................ 3 chs event counter ........ 2 chs (16-bit timer/event counter, carrier generator, timer with gate) ? basic interval timer ... 1 ch ? basic interval timer/watchdog timer ......... 1 ch ? watch timer .......... 1 ch ? watch timer ............................................. 1 ch vectored interrupt ? external : 3 ? external : 3 ? internal : 4 ? internal : 5 test input ? external : 1 ? external : 1 ? internal : 1 ? internal : 1 power supply voltage v dd = 2.7 to 6.0 v v dd = 1.8 to 5.5 v instruction when main system 0.95, 1.91, 3.81, or 15.3 m s ? 0.95, 1.91, 3.81, or 15.3 m s (@ 4.19 mhz) execution time clock is selected (@ 4.19 mhz) ? 0.67, 1.33, 2.67, or 10.7 m s (@ 6.0 mhz) when subsystem 122 m s (@ 32.768 khz) clock is selected package 80-pin plastic qfp (14 x 14 mm) 80-pin plastic qfp 80-pin plastic tqfp (fine pitch) (12 x 12 mm) (14 x 14 mm) 80-pin plastic tqfp (fine pitch) (12 x 12 mm) 80-pin ceramic wqfn
56 m pd75p3036 appendix b. development tools the following development tools have been provided for system development using the m pd75p3036. use the common relocatable assembler for the series together with the device file according to the model. ra75x relocatable assembler host machine part no. (name) os supply medium pc-9800 series ms-dos tm 3.5-inch 2hd m s5a13ra75x ver.3.30 to 5-inch 2hd m s5a10ra75x ver.6.2 note ibm pc/at tm refer to "os for 3.5-inch 2hc m s7b13ra75x or compatible ibm pcs" 5-inch 2hc m s7b10ra75x device file host machine part no. (name) os supply medium pc-9800 series ms-dos 3.5-inch 2hd m s5a13df753036 ver.3.30 to 5-inch 2hd m s5a10df753036 ver.6.2 note ibm pc/at refer to "os for 3.5-inch 2hc m s7b13df753036 or compatible ibm pcs" 5-inch 2hc m s7b10df753036 note ver. 5.00 or later includes a task swapping function, but this software is not able to use that function. remark operations of the assembler and device file are guaranteed only when using the host machine and os described above. * *
m pd75p3036 57 prom write tools hardware pg-1500 this is a prom programmer that can program single-chip microcontroller with prom in stand alone mode or under control of host machine when connected with supplied accessory board and optional programmer adapter. it can also program typical proms in capacities ranging from 256 k to 4 mbits. pa-75p328gc this is a prom programmer adapter for the m pd75p3036gc used by connecting to a pg-1500. pa-75p336gk this is a prom programmer adapter for the m pd75p3036gk used by connecting to a pg-1500. pa-75p3036kk-t note 1 this is a prom programmer adapter for the m pd75p3036kk-t used by connecting to a pg- 1500. software pg-1500 controller connects pg-1500 to host machine with serial and parallel interface and controls pg-1500 on host machine. host machine part no. (name) os supply medium pc-9800 series ms-dos 3.5-inch 2hd m s5a13pg1500 ver.3.30 to 5-inch 2hd m s5a10pg1500 ver.6.2 note 2 ibm pc/at refer to "os for 3.5-inch 2hd m s7b13pg1500 or compatible ibm pcs" 5-inch 2hc m s7b10pg1500 notes 1. under development 2. ver. 5.00 or later includes a task swapping function, but this software is not able to use that function. remark operation of the pg-1500 controller is guaranteed only when using the host machine and os described above. * *
58 m pd75p3036 debugging tools in-circuit emulators (ie-75000-r and ie-75001-r) are provided as program debugging tools for the m pd75p3036. various system configurations using these in-circuit emulators are listed below. hardware ie-75000-r note 1 the ie-75000-r is an in-circuit emulator to be used for hardware and software debugging during development of application systems using the 75x or 75xl series products. for development of the m pd75p3036, the ie-75000-r is used with optional emulation board (ie- 75300-r-em) and emulation probe (ep-753036gc-r or ep-753036gk-r). highly efficient debugging can be performed when connected to host machine and prom programmer. the ie-75000-r includes a connected emulation board (ie-75000-r-em). ie-75001-r the ie-75001-r is an in-circuit emulator to be used for hardware and software debugging during development of application systems using the 75x or 75xl series products. the ie-75001-r is used with optional emulation board (ie-75300-r-em) and emulation probe (ep-753036gc-r or ep-753036gk-r). highly efficient debugging can be performed when connected to host machine and prom programmer. ie-75300-r-em note 2 this is an emulation board for evaluating application systems using the m pd75p3036. it is used in combination with the ie-75000-r or ie-75001-r. ep-75336gc-r this is an emulation probe for the m pd75p3036gc. when being used, it is connected with the ie-75000-r or ie-75001-r and the ie-75300-r-em. ev-9200gc-80 it includes an 80-pin conversion socket (ev-9200gc-80) to facilitate connections with target system. ep-75336gk-r this is an emulation probe for the m pd75p3036gk. when being used, it is connected with the ie-75000-r or ie-75001-r and the ie-75300-r-em. ev-9500gk-80 it includes an 80-pin conversion adapter (ev-9500gk-80) to facilitate connections with target system. software ie control program this program can control the ie-75000-r or ie-75001-r on a host machine when connected to the ie-75000-r or ie-75001-r via an rs-232-c and centronics interface. host machine part no. (name) os supply medium pc-9800 series ms-dos 3.5-inch 2hd m s5a13ie75x ver.3.30 to 5-inch 2hd m s5a10ie75x ver.6.2 note 3 ibm pc/at refer to "os for 3.5-inch 2hc m s7b13ie75x or compatible ibm pcs" 5-inch 2hc m s7b10ie75x notes 1. this is a maintenance product. 2. the ie-75300-r-em is sold separately. 3. ver. 5.00 or later includes a task swapping function, but this software is not able to use that function. remarks 1. operation of the ie control program is guaranteed only when using the host machine and os described above. 2. the m pd753036 and 75p3036 are commonly referred to as the m pd753036 subseries. *
m pd75p3036 59 os for ibm pcs the following operating systems for the ibm pc are supported. os version pc dos tm ver.5.02 to ver.6.3 j6.1/v to j6.3/v ms-dos ver.5.0 to ver.6.22 5.0/v to 6.2/v ibm dos tm j5.02/v caution ver. 5.0 or later includes a task swapping function, but this software is not able to use that function. * *
60 m pd75p3036 appendix c. related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to device document document no. japanese english m pd75p3036 data sheet u11575j u11575e (this document) m pd753036 data sheet u11353j planned m pd753036 users manual u10201j u10201e m pd753036 instruction table iem-5063 75xl series selection guide u10453j u10453e documents related to development tools document document no. japanese english hardware ie-75000-r/ie-75001-r users manual eeu-846 eeu-1416 ie-75300-r-em users manual u11354j eeu-1493 ep-75336gc/gk-r users manual u10644j u10644e pg-1500 users manual eeu-651 eeu-1335 software ra75x assembler package operation eeu-731 eeu-1346 users manual language eeu-730 eeu-1363 pg-1500 controller users manual pc-9800 series eeu-704 eeu-1291 (ms-dos) base ibm pc series eeu-5008 u10540e (pc dos) base other related documents document document no. japanese english ic package manual c10943x semiconductor device mounting technology manual c10535j c10535e quality grades on nec semiconductor devices c11531j c11531e nec semiconductor device reliability/quality control system c10983j c10983e electrostatic discharge (esd) test mem-539 guide to quality assurance for semiconductor devices mei-603 mei-1202 microcomputer C related product guide C third party products C mei-604 caution the related documents listed above are subject to change without notice. be sure to use the latest documents for designing, etc. *
m pd75p3036 61 [memo]
62 m pd75p3036 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
m pd75p3036 63 nec electronics inc. (u.s.) santa clara, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j96. 8
64 m pd75p3036 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5 the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. ms-dos is a trademark of microsoft corporation. ibm dos, pc dos, and pc/at are trademarks of international business machines corporation.

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